`1. (`

`)`

Perform
the following binary additions assuming the numbers are in sign and magnitude
form: 0001 + 0100
1111 + 0010

0011 + 1010

1011 + 1010

`2. (`

`)`

Perform
the same binary additions as in Exercise 5.1, but this time assuming the
numbers are in ones complement form. `3. (`

`)`

Perform
the same binary additions as in Exercise 5.1, but this time assuming the
numbers are in twos complement form. `4. (`

`)`

Implement
a combinational logic circuit that converts 4-bit sign and magnitude numbers
into corresponding 4-bit twos complement numbers. Draw an input/output conversion
truth table, intermediate K-maps, and your minimized two-level logic description.
`5. (`

`)`

`6. (`

`)`

`7. (`

`)`

`8. (`

`)`

Sign
and magnitude and ones complement representations have two zeros, while
twos complement numbers have only one representation for zero. What problem
does this present for converting from twos complement to either of the other
representations? How might this be handled in a practical conversion circuit?
`9. (`

`)`

The truth
table for a 1-bit combinational binary subtractor, analogous to the half
adder, computing `(`

ifference`)`

= `(`

borrow-from-left`)`

,
is
Design a 1-bit combinational binary subtractor, comparable to the full adder, with two data inputs`(`

A,B`)`

, a borrow from the right input`(`

BI`)`

, a borrow request to the left output`(`

BL`)`

, and a difference output`(`

D`)`

.

Show how your design can be cascaded to form multibit-subtractors.

Does the subtractor work correctly for negative twos complement numbers?

How is a subtractionunderflowcondition indicated?

`10. (`

`)`

Design
a fully combinational adder/subtractor that can be cascaded to form a multibit
circuit. The inputs are data inputs BL. A mode input

`11. (`

`)`

Using comparators,
multiplexers, and binary adder/subtractor logic blocks, design a 4-bit sign
and magnitude adder `(`

that is, one sign bit and three data bits`)`

.
Include an overflow indicator in your design. `12. (`

`)`

Design
a combinational circuit with three data inputs `(`

7 divided by 2 yields
a remainder of 1`)`

. - Write the truth table for

Fill in K-maps and write Boolean expressions for

Draw a schematic that implements the functions for

`13. (`

`)`

- Using these as primitive building blocks, show how to construct 32-
and 64-bit adders with carry look-ahead. Draw block diagrams
for the 32- and 64-bit adders, showing all interconnections.

Analyze the worst-case gate delays encountered in 32- and 64-bit addition. Use the simple delay models as in Section 5.2.2.

Using 74LS181 ALUs and 74182 carry look-ahead units for your implementation in part

`(`

a`)`

, determine the typical and worst-case
delays in nanoseconds by referring to your TTL databook.
`14. (`

`)`

with the carry select technique described in Section 5.2.3. The adder is implemented with three 8-bit carry look-ahead adders and eight 2:1 multiplexers. Estimate the gate delay and compare it against a conventional 16-bit ripple adder and a 16-bit carry look-ahead adder.

`15. (`

`)`

Argue why,
using explicit 8-bit test cases, the implementation of `16. (`

`)`

Implement to the
gate level an ALU bit slice with three operation selection inputs, `(`

and carry-in
Cn`)`

:
Assume a simple ripple carry scheme between bit slices.

`17. (`

`)`

Implement to the
gate level an ALU bit slice with three selection inputs, `(`

and carry-in Cn`)`

:
Assume a simple ripple carry scheme between bit slices.

`18. (`

`)`

Revise your design
for the ALU of Exercise 5.16 to include carry look-ahead logic that can
operate across 4 bits. `19. (`

`)`

Revise your design
for the ALU of Exercise 5.17 to include four-bit carry look-ahead logic.
`20. (`

`)`

Describe
how a two-output ROM can be used to implement the ALU bit slice of Figure
5.19. Give a block diagram showing how a 4-bit ALU can be implemented from
four cascaded ROMs. In terms of the total count of ROM bits, how does the
bit slice approach compare with a solution that uses a single ROM with full
4-bit data inputs and outputs? `21. (`

`)`

Verify that the
multilevel circuit of Figure 5.23 implements the ALU specification of Figure
5.18. Do this by expanding the circuit into its equivalent two-level sum
of products expressions for `22. (`

`)`

Perform the following
binary additions assuming the numbers are in BCD form:
- 0001 + 0100

1000 + 1001

0111 + 0011

1001 1001 + 0001 0001

`23. (`

`)`

Design
a 4-bit circuit that can perform either BCD or binary addition under the
control of a mode setting, `24. (`

`)`

Verify
that the operation of the combinational multiplier of Figure 5.28 is correct
by tracing all intermediate signals for the multiplication of 11 `(`

10112`)`

by 13 `(`

11012`)`

. `25. (`

`)`

Verify
that the operation of the combinational multiplier of Figure 5.29 is correct
by tracing all intermediate signals for the multiplication of 11 `(`

10112`)`

by 13 `(`

11012`)`

. `26. (`

`)`

Verify
that the hardware of Figure 5.35 correctly computes the product of 242 by
140 by labeling all outputs with the actual bit patterns that would be computed
at each stage of the circuit. `27. (`

`)`

What
is the worst-case propagation delay through the combinational multiplier
of Figure 5.28, assuming the hardware is implemented with 12 full adders
as in Figure 5.7? `28. (`

`)`

Suppose
that the 8-by-8 multiplier of Figure 5.35 is implemented with three 74S181
ALUs and a 74S182 carry look-ahead unit `(`

the multipliers and
the full adders remain unchanged`)`

. Analyze the typical and
worst-case delays by referring to your TTL databook. How does the delay
compare with those computed at the end of Section 5.6? `29. (`

`)`

Assume
that you have a 4-by-4 -magnitude multiplier available as a primitive building
block. -Discuss the design issues in building a 4-by-4 twos complement multiplier.
Consider such issues as `(`

a`)`

determining the signs
of the inputs and outputs, `(`

b`)`

putting the inputs
into the appropriate form for the magnitude multiplier, and `(`

c`)`

putting the magnitude multiplier's output into a form suitable for twos
complement -representation. `30. (`

`)`

Design
a combinational divider, following the same general approach as used for
the combinational multiplier of Section 5.6. Of course, this time you will
use binary subtractors rather than adders. [Top] [Next] [Prev]