[Top] [Next] [Prev]

6.3 Realizing Circuits with Different Kinds of Flip-Flops

Section 6.1 introduced four different flip-flop types: R-S, J-K, D, and T. In this section, we describe the methods for implementing one kind of flip-flop with another. The procedure is useful because a given flip-flop type may be the best choice to implement a given storage element, but flip-flops of that type may not be available to you.

We already know that a D flip-flop can be formed from a J-K flip-flop: simply tie the set input J to the data input D and the reset input K to . In similar fashion, a T flip-flop can be derived from a J-K flip-flop by connecting both the J and K inputs to T. But in this section, we will develop a general design procedure that will serve as the basis for designing a variety of synchronous sequential circuits in the next -chapter.

6.3.1 Choosing a Flip-Flop Type

In this subsection, we examine the alternative kinds of storage elements for implementing state.

R-S Latch The level-sensitive R-S latch has limited utility as a stand-alone building block for holding state. However, it is used as a component in implementing master/slave or edge-triggered flip-flops, and it serves some special functions for debouncing switches. (See Practical Matters at the end of this chapter.)

J-K Flip-Flops Versus D Flip-Flops In real designs, the most frequently encountered flip-flops are the J-K and the D. The combinational logic associated with determining the next state will often require the fewest gates when the next state function is implemented with J-K flip-flops. However, each J-K flip-flop requires two inputs, and this could lead to more complex wiring. If the goal is to minimize wires, D flip-flops are attractive. In VLSI technologies, where the size of the wiring area is typically a greater concern than gate area, D flip-flops are used almost universally and are usually implemented as cross-coupled inverters as in Figure 6.32.

T Flip-Flops T flip-flops are rarely available in packaged logic because they are so easily formed from J-K flip-flops. From the viewpoint of conceptual design, however, T flip-flops turn out to be good building blocks for special circuits called counters. These are clocked sequential systems that sequence through a periodic series of states, such as the binary numbers 0000 through 1111. We will learn the counter design strategy in the next chapter.

Summary of Flip-Flop Characteristic Equations We have already introduced characteristic equations as a shorthand for describing flip-flop behavior. They are particularly useful when implementing next state logic, by making it possible to relate the desired flip-flop outputs (state) to the inputs that must be generated to obtain the necessary behavior.

If Q is the current state and Q+ is the next state, the equations for the four flip-flop types are

R-S latch: Q+ =
D flip-flop: Q+ = D
-K flip-flop: Q+ =
T flip-flop: Q+ =

6.3.2 Conversion of One Flip-Flop Type to Another

Any flip-flop can be implemented as combinational logic for the next state function in conjunction with a flip-flop of another type.

As an example, Figure 6.40 shows how to implement a D flip-flop with a J-K flip-flop and, correspondingly, a J-K flip-flop with a D flip-flop.

Consider the leftmost circuit. If D is 1, we place the J-K flip-flop in its set input con\xde guration (J = 1, K = 0). If D is 0, J-K's inputs are configured for reset (J = 0, K = 1). In the case of the rightmost circuit, the D flip-flop's input is driven with logic that implements the characteristic equation for the J-K flip-flop, namely .

General Procedure We can follow a general procedure to map among the different kinds of flip-flops. It is based on the concept of an excitation table, that is, a table that lists all possible state transitions and the values of the flip-flop inputs that cause a given transition to take place.

Figure 6.41 gives excitation tables for R-S, J-K, T, and D flip-flops. If the current state is 0 and the next state is to be 0 too, then the first row of the table describes the flip-flop input to cause that state transition to take place. If an R-S latch is being used, it doesn't matter what value is placed on R as long as S is left unasserted. R = 0, S = 0 holds the current state at 0; R = 1, S = 0 resets the state to 0. The effect is the same.

If we are using a J-K flip-flop, the transition from 0 to 0 is accomplished by ensuring that J is left unasserted. The value of K does not matter. If J = 0, K = 0, the current state is held at 0; if J = 0, K = 1, the state is reset to 0.

If we are using a T flip-flop, the transition does not change the current state, so the input should be 0. If a D flip-flop is used, we set the input to the desired next state, which is 0 in this case. The same kind of analysis can be applied to complete the excitation table for the three other cases.

A flip-flop's next state function can be written as a K-map. For example, the next state K-map for the D flip-flop is shown in Figure 6.42(a).

To realize a D flip-flop in terms of a J-K flip-flop, we simply remap the state transitions implied by the D flip-flop's K-map into equations for the J and K inputs. In other words, we express J and K as functions of the current state and D.

The procedure works as follows. First we draw K-maps for J and K, as in Figure 6.42(b). Then we fill them in the following manner. When D = 0 and Q = 0, the next state is 0. The excitation table tells us that the inputs to J and K should be 0 and X, respectively, if we desire a 0-to-0 transition. These values are placed into corresponding entries of the J and K K-maps. The inputs D = 0, Q = 1 lead to a next state of 0. This is a 1-to-0 transition, and J and K should be X and 1, respectively. For D = 1, Q = 0, the transition is from 0 to 1, and J must be 1 and K should be X. The final transition, D = 1, Q = 1, is from 1 to 1, and J and K are X and 0. A quick look at the K-maps confirms that J = D and K = .

The implementation of a J-K flip- flop by a D flip-flop follows the same procedure. We start with a K-map to describe the next state in terms of the three variables J, K, and the current state Q. To obtain the transition from 0 to 0 or 1 to 0 requires that D be 0; similarly, D must be 1 to implement a 0-to-1 or 1-to-1 transition. In other words, the function for D is identical to the next state. The equation for D can be read directly from the next state K-map for the J-K flip-flop:

D =
This K-map is shown in Figure 6.43.

[Top] [Next] [Prev]

This file last updated on 07/14/96 at 15:33:06.